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MC14526BCP
These devices are presettable, cascadable, synchronous down counters with a decoded “0” state output for divide–by–N applications. In single stageapplications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide–by–N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.
Supply Voltage range: 3.0Vdc to 18Vdc
Logic Edge−Clocked Design: Incremented on Positive Transition of Clock or Negative Transistion on Inhibit
Asynchronous Preset Enable