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MC14522B HEP C4042P BCD
These devices are presettable, cascadable, synchronous down counters with a decoded “0” state output for divide–by–N applications. In single stageapplications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide–by–N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.These complementary MOS counters can be used in frequency synthesizers, phase–locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.